The laboratory work was dedicated to CMOS inverters, what they are and how they work. In the first part we learned about CMOS inverters theoretically and then put to the test what we learned. We built our circuits on the breadboard by connecting pins on the PMOS and the NMOS transistors. When the input to a CMOS inverter gate is a 1, then the NMOS transistor turns on and the PMOS transistor turns off, and the output is connected to ground 0. On the contrary, when the input is a 0, then the PMOS transistor turns on and the NMOS transistor turns off, so the output is connected to VDD or 5V.
We also learned about the CMOS NAND (NOT AND) Gate operation. When In1 and In2 are low, then both PMOS transistors are on and both NMOS transistors are off, and the output is about VDD or 5V. When In1 is 0V and In2 is 5V, then PMOS1 transistor is on and NMOS1 transistor is off (but PMOS2 transistor is off and NMOS2 transistor is on), so the output is VDD or 5V. When In1 is 5V and In2 is 0V, then PMOS2 transistor is on and NMOS2 transistor is off (but PMOS1 transistor is off and NMOS1 transistor is on), so the output is VDD or 5V. When In1 and In2 are 5V, then both NMOS Transistors are on and both PMOS transistors are off, so the output is about 0V.
Also, there were some differences between preliminary and measurements results that can be found in many laboratory works. I found that the measured voltage was 5.12V for my laboratory power supply. So the error is: [5 – 5.06] / 5 x100% = 1.2%.
In the end we built the logic NOT OR gate. It means that if at least one input is 1 (true) then there will be no current flow. Otherwise (i.e. only if input1 is 0, input2 is 0, input3 is 0) we will get the current. We needed 3 PMOS and 3 NMOS transistors to make this logic circuit.
